n301/Computer Organization n301.tplt Levels of Abstraction Still hardware At a component (subsystem) level

transistors -->gates -->circuits
circuits -->subsystems

Abstraction hides detail

important concept in my areas of CS

Von Neumann architecture Four major subsystems

memory
input/output (I/O)
arithmetic-logic unit (ALU)
control unit

Stored program concept Sequential fetch-execute cycle Diagram One

The Neumann Architecture Memory Random-access memory - RAM

array of cells, each with address
cell is minimum unit of access
access time is sddress-independent

ROM - Read Only Memory

section of RAM set aside for system software

Memory structure Cell size or width W

generally 8 bits, calles a BYTE
may need multiple cells to store large numbers or long program instructions

Cell content vs. cell address Memory Registers Special (large) storage cells (1) Memory address register - MAR

holds cell address
N bits wide

(2) Memory data register - MDR

holds data values
multiple of W

Diagram Two

Structure of Random Access Memory Address space Instructions refers to cell addresses

stored in binary form

Suppose N bits for address

can represent numbers in range 0 to 1 1 ... 1 = 2^N - 1
determines memory size, 2^N
"address space"

Basic memory operations (1) Fetch (address)"Read"

load address into MAR
decode address
copy contents of cell at that address into MDR
nondestructive operation

Basic memory operations - 2 (2) Store (address, value) "Write"

load address into MAR
load value into MDR
decode address
store contents of MDR into cell with that address
destructive operation

Decode address Convert a string of N bits (on N bits (on N input lines) to a signal on a single output line This is a decoder To scale up, use a 2-dimensional arrangement Diagram Three

Organization of Memory and Decoding Logic Diagram Four

Two-Dimensional Memory Organization Diagram Five

Overall RAM Organization I/O Human-machine interface

keyboard, screen, printer

Machine-machine interface

mass storage, secondary storage
floppy disks, hard disks, CDs, tape

The most nonstandard subsystems ALU "the brain" Seperate, high-speed-access registers

storage for operands

Obtain operands from registers, store result in register by activating correct BUS ALU operation Add, subtract, multiply, divide, compare Circuits for each operation

we saw add circuit

Each operation is done! Select the result you want

Muliplexor

Diagram Six

Three-Register ALU Organization Diagram Seven

Multiregister ALU Organization Diagram Eight

Using a Multiplexor Circuit to Select the Proper ALU Result Diagram Nine

Overall ALU Organization The Control Unit (CU) fetch Memory (instruction) decode execute --> (ALU) store Machine Language Instructions

Opcode	Addn 1	Addn 2
What kind of operation.	Where data comes from/result goes to.

The Instruction Set: Group 1 Data Transfer These are operations that move information between or within the different components of the computer.

Memory cell --> ALU register
ALU register --> memory cell
One memory cell --> another memory cell
One ALU register --> another ALU register

The Instruction Set: Group 2 Arithmetic These are operations that causes the arithmetic/logic unit to perform a computation.

+
-
X
/
AND
OR
NOT

The Instruction Set: Group 3 Compare These operations compare two values and set an indicator on the basis of the results of the compare.

condition codes - special set of bits set by the compare operation.

The Instruction Set: Group 4 Brach Alters the normal sequential flow of control Diagram 10a

Diagram 10b

Diagram 10c

Diagram 11

Organization of the Control Unit Registers and Circuits Diagram 12

The Instruction Decoder Diagram 13

The Organization of a Von Neumann Computer